The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict\r\nlikely yield. Monte-Carlo- (MC-) and quasi-MC- (QMC-) based statistical techniques do this by analysing many randomised or\r\nquasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology,\r\nincluding ââ?¬Å?atomisticââ?¬Â effects without intradie correlation and effects with intradie correlation between neighbouring devices.\r\nA major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use\r\nof principal components analysis, behavioural modeling, and an implementation of ââ?¬Å?Statistical Blockadeââ?¬Â (SB) is shown to be\r\ncapable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for\r\na commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction,\r\nand this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The\r\nââ?¬Å?yield predictionââ?¬Â analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using\r\nparameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained.
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